Measuring Power Plane Impedance Flatness and POL Stability

With the increase in current slew rates within modern FPGAs and high-density digital platforms, the objective of power distribution network (PDN) design has evolved to ensuring that impedance remains flat and well-damped versus frequency.

Although many point-of-load (POL) reference designs satisfy datasheet transient specifications in isolation, their stability margins often erode when coupled to the distributed impedance of real PCB power planes. Recent industry surveys suggest that a substantial portion of POL reference designs, on the order of forty percent, may operate near the boundary of instability when subjected to realistic PDN conditions.

This paper details how you can use a low-frequency VNA to identify resonant characteristics and damping behavior across the operational spectrum by measuring power-plane impedance as a function of frequency. It explores:

PDN impedance and stability fundamentals
Why low-frequency measurement matters (9 kHz – 10 MHz Region)
Measuring power plane impedance with a VNA
Plane impedance and system stability
Closed-Loop stability measurement using VNA perturbation

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Date: 1.8.2018

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